\section{Simulation}
The directory \textit{firmware/simulation/pcie\_dma\_top} contains all necessary files to run the simulation in Mentor Graphics Modelsim or Questasim \cite{questasim}. 

\subsection{Prerequisites}
The directory contains a file modelsim.ini with some standard information, it is assumed that one have the Xilinx Unisim\_VCOMPONENTS library compiled and the location is defined in the environment variable \$XILLIB. Also the Library "work" has to be created in the project directory.

The simulation project also relies on a simulation model of the FIFOcore, which will be generated when the cores in the Vivado project are generated. The file that should be generated is \textit{../../Projects/pcie\_dma\_top/pcie\_dma\_top.srcs/sources\_1/ip/fifo\_generator\_0 /fifo\_generator\_0\_funcsim.vhdl}

\subsection{Creating the project and running the simulation.}
Like the Vivado project, also the Questasim project is generated and operated using .tcl scripts. To create and run the project execute the following commands from a bash console. Make sure that vsim is in the path, UVVM and xilinx\_simlib are compiled in the firmware/simulation directory:
\begin{lstlisting}[language=tcl, frame=single, caption=Run the simulation]
cd firmware/simulation/Wupper/
./ci.sh Wupper
\end{lstlisting}
The project does not include the actual Xilinx PCIe core simulation model, but the AXI4-Stream interface is simulated by a behavioral simulation model.
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